As opposed to static random access memories (SRAM) in which the information stored remains so stored indefinitely at least for as long as this memory remains energized, dynamic memories exhibit the feature of requiring a periodic refreshing of the information stored. This is so because of the stray leakage currents which discharge the storage capacitance of each memory cell. Among dynamic random access memory cells, mention may be made in particular of those comprising two or three transistors, and those comprising a single transistor. For these types, the stored information is destroyed by reading.
Conventionally, dynamic random access memories are laid out in rows and columns of memory cells and comprise, for each column, an amplification device for reading/rewriting each memory cell selected. The memory also includes precharge means making it possible to precharge the corresponding column of the matrix (commonly termed a "Bit Line" by those skilled in the art) to a chosen voltage level. The device also includes amplification means comprising two looped-back inverters (forming a bistable flip-flop) each formed by two complementary transistors and controlled by two successive signals, read and rewrite (commonly known respectively as "sense" and "restore").
Conventionally, these two inverters are connected together directly head-to-tail and this may lead to erroneous refreshing of the memory cell if, while reading, the voltage difference between the bit line and the bit line of the immediately adjacent column (serving as reference) is less than the offset voltage of the amplifier.